One embodiment of the invention relates to a method for fabricating field-effect transistor structures with gate electrode structures each having a metal layer.
Integrated circuits include field-effect transistor structures each having an active area and a gate electrode. The active area comprises a source region, a drain region and a channel region between the source and drain regions. The source region and the drain region are formed in a semiconductor substrate as doped regions of a first conductivity type in each case below a process surface of the semiconductor substrate. The channel region is in the form of an undoped region or a doped region of a second conductivity type which is opposite to the first conductivity type. The gate electrodes of the field-effect transistor structures are in each case provided above the channel region on a gate dielectric resting on the process surface of the semiconductor substrate.
When the field-effect transistor structure is operating, the formation of a conductive channel in the channel region between the source region and the drain region is controlled by a potential at the gate electrode.
To form the gate electrodes of the field-effect transistors, first of all a sequence of layers of a gate electrode layer stack is deposited on the gate dielectric layer, and then the gate electrode layer stack is patterned by means of a photolithographic process.
In memory cell arrays, the gate electrodes of a plurality of select transistors of the memory cells form integral components of word lines for addressing the memory cells in the memory cell array. Since the access times of the memory cells depend on the conductivity of the word lines, it is aimed to use materials with a low resistivity to form the gate electrodes.
It is customary, for example, to provide tungsten for a metal layer in the gate electrode layer stack. Metal atoms which diffuse out of the respective metal layer act as impurities in adjacent structures which do not contain metal, having an adverse effect, for example, on the insulator properties of these structures. Therefore, at least in the direction of the gate dielectric, a barrier layer preventing metal atoms from diffusing into adjacent structures is provided as a sublayer, of the metal layer. For functional reasons, a polysilicon layer is used in the vicinity in the gate dielectric.
U.S. Pat. No. 6,198,144 has disclosed a gate electrode structure that includes an polysilicon layer resting on the gate dielectric, an electrically conductive barrier layer on the polysilicon layer and a metal layer on the barrier layer. The metal of the metal layer is tungsten. The barrier layer is formed from tungsten nitride. A silicon dioxide layer as an insulating cap layer rests on the metal layer. The vertical side walls of the gate electrode structures are each covered by a silicon nitride coating.
One significant aspect in the processing of gate electrode structures or gate stacks is the height of the gate electrode structure (stack height). The general aim is to reduce the stack height, since as the aspect ratio of the gate electrode structures and of the trenches between the gate electrode structures rises, various processes involved in forming field-effect transistors become more difficult. This is true in particular of the etching involved in opening a mask in order to pattern the gate electrode layer stack, the etching of the gate electrode layer stack itself, the filling of trenches between the gate electrode layer stacks, the etching of the fillings for contact-connection of the source or drain regions of the field-effect transistors, the deposition of a barrier layer for metallic contact structures in the trenches and the deposition of metal for forming the contact structures.
The source and drain regions are formed by implantation with masking by the gate stacks. To improve the functionality of the select transistors as memory cells, it is known to use an oblique implantation to form doped regions which are asymmetric and/or considerably undercut the gate stacks. As the height of the gate stacks increases, the possible range for an implantation angle at which the oblique implantation is carried out becomes narrower.
Reducing the thickness of the metal layer leads to an increase in the resistance of the word line. The proportion of the total height of the gate stack that is formed by the barrier layers is relatively small. For process engineering reasons, the thickness of the polysilicon layer is substantially dependent on the standard patterning of the gate electrode layer stack.
In general, the etching of the gate electrode layer stack is carried out in at least two etching steps, with the first etching step acting on the metal-containing layers and the second etching step acting on the polysilicon layer.
To ensure the complete removal of the metal-containing layers outside the gate stack structure, the metal-containing layers are overetched; a correspondingly high thickness of the polysilicon layer ensures that the etching step is guaranteed to end in the region of the polysilicon layer. Furthermore, the metal-containing layers are generally covered with a nitride liner prior to the etching of the polysilicon layer. Further overetching into the polysilicon layer, resulting in the need for an additional reserve in the layer thickness of the polysilicon layer, is required to reliably open up the nitride liner above the polysilicon.
Therefore, the polysilicon layer is generally provided in a significantly greater layer thickness than its electrical functionality in the finished field-effect transistor structure required. The etching processes required for patterning of the gate electrode layer stack are relatively complex and lead to the processing of structures with a high aspect ratio.